Synplify pro power report how to#

Once you have found a bug, you can fix it incrementally in the RTL or constraints, using hierarchical and incremental flows. You can write the observed sampled data to a VCD file and relate it back to the RTL. As you run your tests on the board, the watchpoints and breakpoints together will trigger data sampling, allowing you to observe and debug the circuitвЂ™s behavior at very specific nodes under very specific conditions of interest.

After you have synthesized the design, run the design and observe the data using the RTL debugger. Synthesize the FPGA design with additional monitoring circuitry: an intelligent in-circuit emulator (IICE), which captures and exports debug data according to the specification of what you wanted to monitor. Here you state watchpoints (signals or nodes to be observed) and breakpoints (RTL control flow statements such as IF, THEN and CASE statements) whose operation is of interest to you. Specify within the RTL exactly what signals and conditions you want to monitor. You can then relate your observations back to the original RTL to narrow down the cause of the problem, which may reside in the RTL specification or constraints setup.

Synplify pro power report how to#

LetвЂ™s examine how to find errors using board-level debug software.Д«y following a four-step approach with an RTL debugger, you can pinpoint and then sample signals and conditions of interest. To debug the design, it is necessary to create additional circuitry and preserve certain nodes so that you can probe, tap and analyze data produced by the design under operation. When functional errors become apparent on the board, it may be quite challenging to narrow down the cause of the problem. Such tools include features that enable designers to quickly isolate bugs and effectively reduce the length of runtimes and the number of iterations needed to bring up their boards. SynopsysвЂ™ Synplify Premier and Synplify Pro FPGA design tools and Identify RTL Debugger are among the products available to designers to handle these tasks. You can save time by performing rudimentary design setup checks on clocks, constraints and module-level interfaces with a view to making your design specification good, before you waste hours in synthesis and place-and-route (P&R). It is essential to apply smarter techniques to isolate specific errors under specific conditions, relate parts of the circuit that are behaving badly back to the source and apply the incremental fixes. Given how lengthy FPGA design iterations and runtimes have become, designers need to find and root out what may be a large group of errors early in the design process and seek methods to focus the validation of the design on the board. When your FPGA design fails to synthesize or fails to operate as expected on the board, the cause may not be obvious and the source of the failure may be hard to pinpoint among potentially thousands of RTL and constraint source files, many of which may have been authored by another designer. Editor's Note: This article appeared in the autumn 2012 edition of Xcell Journal magazine, and is reproduced here with the kind permission of Mike Santarini, Publisher and Senior Manager, Xcell Journal and Editorial Services, Worldwide Communications, Xilinx.